About
Blog
Popular
Subscriptions
Help
Donate
Contact
eBook
mela
Collections
Books
Video
Audio
Software
Images
All
Open search
Library
Cart
Toggle theme
Open menu
Home
Books
Video
Audio
Library
Library
Texts
en_US eng
Multiple-valued programmable logic array minimization by sim...
4.8
Free Access
Read
Download Options
Get Hardcopy
Buy from
Amazon
texts
en_US eng
1992
Uploaded by
TheMikeBest
Multiple-valued programmable logic array minimization by simulated annealing
Dueck Gerard W ;Earle Robert C ;Tirumalai Parthasarathy ;Butler Jon T
191.9K
Followers
·
77
Books
4.8
Rating
2.8K
Reviews
12.4K
Favorites
892K
Views
58.2K
Downloads
OVERVIEW
Library Tags
ANNEALING
COMPUTER AIDED DESIGN
COMPUTERIZED SIMULATION
LOGIC CIRCUITS
COMPUTER PROGRAMS
Bibliographic Information
Title
Multiple-valued programmable logic array minimization by simulated annealing
Creator
Dueck Gerard W ;Earle Robert C ;Tirumalai Parthasarathy ;Butler Jon T
Topic
ANNEALING
,
COMPUTER AIDED DESIGN
,
COMPUTERIZED SIMULATION
,
LOGIC CIRCUITS
,
COMPUTER PROGRAMS
Date
1992-01-01T00:00:00Z
Publisher
Monterey, California : Naval Postgraduate School
Language
En_US eng
collection added
Usgovernmentmirrors
,
Government Documents
Download Vault
DJVU
1 Options
DJVUTXT
1 Options
TEXT PDF
Searchable Archival Document
1 Options
0 Comments
Sort by
Multiple-valued programmable logic array minimization by simulated annealing by Dueck Gerard W ;Earle Robert C ;Tirumalai Parthasarathy ;Butler Jon T - Free PDF Download & Read Online | eBookmela
